Guillume DIDIER
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843cf63ba9
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Add preliminary support for IP control
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2021-10-13 15:39:05 +02:00 |
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Guillume DIDIER
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b2f7a80395
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Fix compile issues
This is a stop gap solution selecting the calibration strategy at compile time.
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2021-10-13 14:40:41 +02:00 |
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Guillume DIDIER
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27d592274c
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Stub the module in charge of controlling instruction pointers
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2021-10-13 13:53:20 +02:00 |
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Guillume DIDIER
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8d78c70dae
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Rust Update, clean up MMappedMemory
Ensure the code compiles with the latest rust nightly version, and fixes some unsafety in MMappedMemory
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2021-09-20 14:45:40 +02:00 |
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Guillaume DIDIER
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c12a3ba29b
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Fix missing --bin in cargo invocation
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2021-08-02 15:57:52 +02:00 |
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Guillume DIDIER
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0e60fd62ba
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Add missing scripts
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2021-08-02 15:53:58 +02:00 |
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Guillume DIDIER
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bf931bfa52
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Various experiments
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2021-08-02 15:02:52 +02:00 |
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Guillume DIDIER
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84cf28f21c
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Reproduce the pattern from the other paper
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2021-07-25 10:01:41 +02:00 |
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Guillume DIDIER
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3f0f12d118
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Tweaks that reduce overhead and show prefetch occuring where expected
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2021-07-21 17:29:18 +02:00 |
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Guillume DIDIER
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2d179897bf
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More test cases
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2021-07-19 11:33:17 +02:00 |
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Guillume DIDIER
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e4940abe82
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Update Display for FullPageDualProbeResults
This now has proper header and table alignment.
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2021-07-19 10:54:30 +02:00 |
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Guillume DIDIER
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bf347f7a12
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Switch back to improved F+R
The channel claibration issue ought to be fixed by 4cbacf96
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2021-07-19 09:47:35 +02:00 |
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Guillume DIDIER
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3022794752
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Hotfix - Use naive F+R instead of F+R
F+R currently has a calibration bug
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2021-07-19 09:02:08 +02:00 |
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Guillume DIDIER
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b7b5cbbfc3
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Update the cache channel interface
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2021-06-28 16:26:02 +02:00 |
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Guillume DIDIER
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1b38b4913c
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Commit prefetcher reverse work
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2021-06-10 11:25:07 +02:00 |
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Guillume DIDIER
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4bc389272f
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Start working on prefetcher reverse engineering experiment
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2021-03-22 16:13:01 +01:00 |
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