TP05b (buggy)
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@ -6,14 +6,14 @@ Functions to convert a CFG out of SSA Form.
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from typing import cast, List
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from Lib import RiscV
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from Lib.CFG import Block, BlockInstr, CFG
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from Lib.Operands import Temporary
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from Lib.Operands import Temporary, DataLocation
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from Lib.Statement import AbsoluteJump, Label
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from Lib.Terminator import BranchingTerminator, Return
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from Lib.PhiNode import PhiNode
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from TP05.SequentializeMoves import sequentialize_moves
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from TP05.SequentializeMoves import sequentialize_moves, generate_smart_move
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def generate_moves_from_phis(phis: List[PhiNode], parent: Block) -> List[BlockInstr]:
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def generate_moves_from_phis(phis: List[PhiNode], parent: Block, is_smart: bool=False) -> List[BlockInstr]:
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"""
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`generate_moves_from_phis(phis, parent)` builds a list of move instructions
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to be inserted in a new block between `parent` and the block with phi nodes
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@ -22,11 +22,30 @@ def generate_moves_from_phis(phis: List[PhiNode], parent: Block) -> List[BlockIn
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This is an helper function called during SSA exit.
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"""
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# (Lab 5a, Exercise 6)
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lbl = parent.get_label()
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if is_smart:
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parallel_moves: set[tuple[DataLocation, DataLocation]] = set()
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moves: List[BlockInstr] = []
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for phi in phis:
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if lbl not in phi.get_srcs():
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continue
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src = phi.get_srcs()[lbl]
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if isinstance(src, Temporary) or isinstance(phi.var, Temporary):
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loc1, loc2 = phi.var, src
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if isinstance(loc1, Temporary):
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loc1 = loc1.get_alloced_loc()
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if isinstance(loc2, Temporary):
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loc2 = loc2.get_alloced_loc()
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moves += generate_smart_move(loc1, cast(DataLocation, loc2))
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else:
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src = phi.get_srcs()[lbl]
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parallel_moves.add((phi.var, cast(DataLocation, src)))
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return sequentialize_moves(parallel_moves)+moves
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return [
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RiscV.mv(
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phi.defined()[0],
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phi.get_srcs()[parent.get_label()]
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) for phi in phis if parent.get_label() in phi.get_srcs()
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phi.var,
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phi.get_srcs()[lbl]
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) for phi in phis if lbl in phi.get_srcs()
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]
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@ -43,7 +62,7 @@ def exit_ssa(cfg: CFG, is_smart: bool) -> None:
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for parent in parents:
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# Add the block containing 'moves' to 'cfg'
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moves_label = cfg.fdata.fresh_label("merge_phi")
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block_moves = Block(moves_label, generate_moves_from_phis(phis, parent), AbsoluteJump(b.get_label()))
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block_moves = Block(moves_label, generate_moves_from_phis(phis, parent, is_smart=is_smart), AbsoluteJump(b.get_label()))
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cfg.add_block(block_moves)
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# Update parent terminator
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@ -1,6 +1,6 @@
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from typing import Dict, Set, Tuple
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from Lib.Operands import Temporary
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from Lib.Statement import Statement, regset_to_string
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from Lib.Statement import Statement, regset_to_string, Instru3A
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from Lib.CFG import Block, CFG
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from Lib.PhiNode import PhiNode
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@ -35,16 +35,41 @@ class LivenessSSA:
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def livein_at_instruction(self, block: Block, pos: int, var: Temporary) -> None:
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"""Backward propagation of liveness information at the beginning of an instruction."""
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raise NotImplementedError("LivenessSSA") # TODO (Lab 5b, Exercise 1)
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instr = block.get_all_statements()[pos]
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if isinstance(instr, PhiNode) and var in instr.srcs.values():
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bpred = self._cfg.get_block(
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next(lbl for lbl, value in instr.srcs.items() if value == var)
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)
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self.liveout_at_block(bpred, var)
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elif pos == 0:
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for bpred in block.get_in():
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self.liveout_at_block(bpred, var)
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else:
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self.liveout_at_instruction(block, pos-1, var)
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def liveout_at_instruction(self, block: Block, pos: int, var: Temporary) -> None:
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"""Backward propagation of liveness information at the end of an instruction."""
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instr = block.get_all_statements()[pos]
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raise NotImplementedError("LivenessSSA") # TODO (Lab 5b, Exercise 1)
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self._liveout[block, instr].add(var)
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if var in instr.defined():
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#self._seen[block].add(var)
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return
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self.livein_at_instruction(block, pos, var)
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#self._seen[block].add(var)
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def liveout_at_block(self, block: Block, var: Temporary) -> None:
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"""Backward propagation of liveness information at the end of a block."""
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raise NotImplementedError("LivenessSSA") # TODO (Lab 5b, Exercise 1)
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if var not in self._seen[block]:
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self._seen[block].add(var)
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self.liveout_at_instruction(block, len(block.get_all_statements())-1, var)
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def gather_uses(self) -> Dict[Temporary, Set[Tuple[Block, int]]]:
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"""
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@ -67,7 +92,9 @@ class LivenessSSA:
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def conflict_on_phis(self) -> None:
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"""Ensures that variables defined by φ instructions are in conflict with one-another."""
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raise NotImplementedError("LivenessSSA") # TODO (Lab 5b, Exercise 1)
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for block in self._cfg.get_blocks():
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for phinode in block.get_phis():
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self._liveout[block, phinode] = set([v for v in phinode.used() if isinstance(v, Temporary)])
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def print_map_in_out(self) -> None: # pragma: no cover
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"""Print live out sets at each instruction, group by block, useful for debugging!"""
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@ -18,8 +18,22 @@ def generate_smart_move(dest: DataLocation, src: DataLocation) -> List[BlockInst
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This is an helper function for `sequentialize_moves`.
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"""
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instr: List[BlockInstr] = []
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# TODO Compute the moves (Lab 5b, Exercise 4)
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raise NotImplementedError("generate_smart_move")
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tmp: Register = S[1]
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match dest, src:
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case Register(), Register():
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if dest != src:
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instr.append(RiscV.mv(dest, src))
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case Register(), Offset():
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instr.append(RiscV.ld(dest, src))
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case Offset(), Register():
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instr.append(RiscV.sd(src, dest))
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case Offset(), Offset():
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instr.append(RiscV.ld(tmp, src))
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instr.append(RiscV.sd(tmp, dest))
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case _, _:
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raise ValueError(f"Unsupported operands {type(dest)} <- {type(src)}")
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return instr
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@ -40,18 +54,27 @@ def sequentialize_moves(parallel_moves: Set[Tuple[DataLocation, DataLocation]]
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# List for the sequentialized moves to do
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# Convention: in moves we put (dest, src) for each move
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moves: List[Tuple[DataLocation, DataLocation]] = []
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# First iteratively remove all the vetices without successors
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# First iteratively remove all the vertices without successors
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vars_without_successor = {src
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for src, dests in move_graph.neighbourhoods()
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if len(dests) == 0}
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while vars_without_successor:
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# TODO Remove the leaves iteratively (Lab 5b, Exercise 4)
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raise NotImplementedError("sequentialize_moves: leaves")
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var = vars_without_successor.pop()
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for src in move_graph.pred(var):
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moves.append((var, src))
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dests = [dests for sr, dests in move_graph.neighbourhoods() if sr == src][0]
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if len(dests) == 1:
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vars_without_successor.add(src)
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move_graph.delete_vertex(var)
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# Then handle the cycles
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cycles: List = move_graph.connected_components()
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for cycle in cycles:
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# TODO Handle each cycle (Lab 5b, Exercise 4)
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raise NotImplementedError("sequentialize_moves: cycles")
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previous = tmp
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for var in reversed(cycle):
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moves.append((previous, var))
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previous = var
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moves.append((previous, tmp))
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# Transform the moves to do in actual RiscV instructions
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moves_instr: List[BlockInstr] = []
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for dest, src in moves:
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@ -1,11 +1,12 @@
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from typing import List, Dict
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from Lib.Errors import MiniCInternalError
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from Lib.Operands import Temporary, Operand, S, Offset, DataLocation, GP_REGS
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from Lib.Statement import Instruction
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from Lib.Statement import Instruction, Instru3A
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from Lib.Allocator import Allocator
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from Lib.FunctionData import FunctionData
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from Lib import RiscV
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from Lib.Graphes import Graph # For Graph coloring utility functions
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from TP05.SequentializeMoves import generate_smart_move
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class SmartAllocator(Allocator):
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@ -28,9 +29,27 @@ class SmartAllocator(Allocator):
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before: List[Instruction] = []
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after: List[Instruction] = []
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new_args: List[Operand] = []
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# TODO (lab5): Compute before, after, subst. This is similar to what
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# TODO (lab5): replace from the Naive and AllInMem Allocators do (Lab 4).
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raise NotImplementedError("Smart Replace (lab5)") # TODO
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for arg in old_instr.defined():
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match arg:
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case Offset():
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after.append(RiscV.sd(S[3], arg))
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new_args.append(S[3])
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case Temporary():
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new_args.append(arg.get_alloced_loc())
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case _: # Contains Register()
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new_args.append(arg)
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for i, arg in enumerate(old_instr.used(), 1):
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match arg:
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case Offset():
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before.append(RiscV.ld(S[i], arg))
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new_args.append(S[i])
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case Temporary():
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new_args.append(arg.get_alloced_loc())
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case _: # Contains Register()
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new_args.append(arg)
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# And now return the new list!
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instr = old_instr.with_args(new_args)
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return before + [instr] + after
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@ -70,7 +89,12 @@ class SmartAllocator(Allocator):
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# Iterate over self._liveness._liveout (dictionary containing all
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# live out temporaries for each instruction), and for each conflict use
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# self._igraph.add_edge((t1, t2)) to add the corresponding edge.
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raise NotImplementedError("build_interference_graph (lab5)") # TODO
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for (block, statement), vars in self._liveness._liveout.items():
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for t1 in list(vars)+statement.defined():
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for t2 in vars:
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if t1 == t2:
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continue
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self._igraph.add_edge((t1, t2))
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def smart_alloc(self) -> None:
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"""
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@ -79,6 +103,7 @@ class SmartAllocator(Allocator):
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Precondition: the interference graph _igraph must have been built.
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"""
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regs = list(GP_REGS) # Get a writable copy
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# Checking the interference graph has been built
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if not self._igraph:
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raise MiniCInternalError("Empty interference graph in the Smart Allocator")
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@ -92,7 +117,15 @@ class SmartAllocator(Allocator):
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alloc_dict: Dict[Temporary, DataLocation] = dict()
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# Use the coloring `coloringreg` to fill `alloc_dict`.
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# Our version is less than 5 lines of code.
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raise NotImplementedError("Allocation based on graph coloring (lab5)") # TODO
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color_dict: Dict[int, DataLocation] = dict()
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for temp in self._fdata._pool.get_all_temps():
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if coloringreg[temp] not in color_dict:
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color_dict[coloringreg[temp]] = (
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regs.pop() if len(regs) > 0 else
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self._fdata.fresh_offset()
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)
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alloc_dict[temp] = color_dict[coloringreg[temp]]
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if self._debug:
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print("Allocation:")
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print(alloc_dict)
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