@misc{flushflush,
      title={Flush+Flush: A Fast and Stealthy Cache Attack}, 
      author={Daniel Gruss and Clémentine Maurice and Klaus Wagner and Stefan Mangard},
      year={2016},
      eprint={1511.04594},
      archivePrefix={arXiv},
      primaryClass={cs.CR},
      url={https://arxiv.org/abs/1511.04594}, 
}

@InProceedings{calibrationdoneright,
      author="Didier, Guillaume
      and Maurice, Cl{\'e}mentine",
      editor="Bilge, Leyla
      and Cavallaro, Lorenzo
      and Pellegrino, Giancarlo
      and Neves, Nuno",
      title="Calibration Done Right: Noiseless Flush+Flush Attacks",
      booktitle="Detection of Intrusions and Malware, and Vulnerability Assessment",
      year="2021",
      publisher="Springer International Publishing",
      address="Cham",
      pages="278--298",
      abstract="Caches leak information through timing measurements and side-channel attacks. Several attack primitives exist with different requirements and trade-offs. Flush+Flush is a stealthy and fast one that uses the timing of the clflush instruction depending on whether a line is cached. We show that the CPU interconnect plays a bigger role than previously thought in these timings and in Flush+Flush error rate.",
      isbn="978-3-030-80825-9",
      url={https://doi.org/10.1007/978-3-030-80825-9_14}
}