Update main.py

This commit is contained in:
augustin64 2024-06-12 11:07:30 +02:00
parent 8e8f9995a8
commit 3f2021b065
2 changed files with 29 additions and 17 deletions

View File

@ -1,28 +1,29 @@
# Machines sélectionnées
- [ ] ~~grenoble/dahu~~ (x32) : 2 procs, 32 cores (default) : Skylake
- [ ] ~~grenoble/troll~~ (x4) : 2 procs, 32 cores (default) : Cascade Lake-SP
- [ ] ~~grenoble/dahu~~ (x32): 2p 32c (deft) : Xeon Gold 6130 [Skylake]
- [ ] ~~grenoble/troll~~ (x4) : 2p 32c (deft) : Xeon Gold 5218 [Cascade Lake-SP]
- [ ] ~~lille/chirop~~ (x5) : 2 procs, 64 cores (testing) : Ice Lake
- [ ] ~~lille/chirop~~ (x5) : 2p 64c (test) : Xeon Platinum 8358 [Ice Lake]
- [x] lyon/nova (x22) : 2 procs, 16 cores (default) : Broadwell Intel Xeon E5-2620 v4
- [x] lyon/nova (x22): 2p 16c (deft) : Xeon E5-2620 v4 [Broadwell]
- [ ] ~~nancy/graffiti~~ (x13) : 2 procs, 16 cores (production) : Skylake
- [ ] ~~nancy/grvingt~~ (x64) : 2 procs, 32 cores (production) : Skylake
- [ ] ~~nancy/graffiti~~ (x13): 2p 16c (prod) : Xeon Silver 4110 [Skylake]
- [ ] ~~nancy/grvingt~~ (x64): 2p 32c (prod) : Xeon Gold 6130 [Skylake]
- [ ] nantes/econome (x22) : 2 procs, 16 cores (default) : Sandy Bridge Intel Xeon E5-2620 v4
- [ ] nantes/econome (x22): 2p 16c (deft) : Xeon E5-2660 [Sandy Bridge]
- [x] rennes/paravance (x72) : 2 procs, 16 cores (default) : Haswell Intel Xeon E5-2630 v3
- [x] rennes/parasilo (x27) : 2 procs, 16 cores (default) : Haswell Intel Xeon E5-2630 v3
- [x] rennes/roazhon12 (x4) : 2 procs, 16 cores (production) : Sandy Bridge Intel Xeon E5-2660
- [ ] rennes/roazhon11 (x3) : 2 procs, 16 cores (production) : Sandy Bridge Intel Xeon E5-2660
- [x] rennes/abacus2 (x1) : 2 procs, 16 cores (production) : Sandy Bridge Intel Xeon E5-2609 v4
- [ ] rennes/abacus3 (x1) : 2 procs, 16 cores (production) : Broadwell Intel Xeon E5-2620 v4
- [ ] ~~rennes/roazhon3~~ (x1) : 2 procs, 32 cores (production) : Skylake Intel Xeon Gold 6142
- [x] rennes/abacus2 (x1) : 2p 16c (prod) : Xeon E5-2609 v4 [Sandy Bridge]
- [ ] rennes/abacus3 (x1) : 2p 16c (prod) : Xeon E5-2620 v4 [Broadwell]
- [x] rennes/parasilo (x27): 2p 16c (deft) : Xeon E5-2630 v3 [Haswell]
- [x] rennes/paravance (x72): 2p 16c (deft) : Xeon E5-2630 v3 [Haswell]
- [x] rennes/roazhon11 (x3) : 2p 16c (prod) : Xeon E5-2660 [Sandy Bridge]
- [ ] rennes/roazhon12 (x4) : 2p 16c (prod) : Xeon E5-2660 [Sandy Bridge]
- [ ] ~~strasbourg/fleckenstein~~ (x10) : 2 procs, 32 cores (testing) : Ice Lake
- [ ] ~~rennes/roazhon3~~ (x1) : 2p 32c (prod) : Xeon Gold 6142 [Skylake]
- [ ] ~~toulouse/montcalm~~ (x10) : 2 procs, 32 cores (default) : Ice Lake
- [ ] ~~strasbourg/fleckenstein~~ (x10): 2p 32c (test) : Xeon Silver 4314 [Ice Lake]
- [ ] ~~toulouse/montcalm~~ (x10): 2p 32c (deft) : Xeon Silver 4314 [Ice Lake]
On n'utilise pas les machines Ice Lake, Sky Lake, CascadeLake pour le moment.
Il faut penser à récupérer family model stepping (`lstopo --of xml` suffira)

13
main.py
View File

@ -39,8 +39,19 @@ def search_site(SITE):
platform_type = item["architecture"]["platform_type"]
proc_vendor = item["processor"]["vendor"]
microarch = item["processor"]["microarchitecture"]
proc_desc = item["processor"]["model"] +" "+str(item["processor"].get("version", ""))
queue = {
"production": "prod",
"default": "deft",
"testing": "test",
}[[q for q in node["queues"] if q != "admin"][0]]
if nb_procs == 2 and math.log2(nb_cores).is_integer() and platform_type == "x86_64" and proc_vendor.lower() == "intel":
print(f"{SITE}/{uid} (x{len(data['items'])}) : {nb_procs} procs, {nb_cores} cores (queues : {node['queues']}) : {microarch}")
print(
f"{SITE}/{uid}".ljust(24)
+f"(x{len(data['items'])})".ljust(5)
+f": {nb_procs}p {nb_cores}c ({queue})".ljust(15)
+f": {proc_desc: <24} [{microarch}]"
)
if len(sys.argv) > 1: