Commit Graph

15 Commits

Author SHA1 Message Date
Guillume DIDIER
8d78c70dae Rust Update, clean up MMappedMemory
Ensure the code compiles with the latest rust nightly version, and fixes some unsafety in MMappedMemory
2021-09-20 14:45:40 +02:00
Guillume DIDIER
4bc389272f Start working on prefetcher reverse engineering experiment 2021-03-22 16:13:01 +01:00
Guillume DIDIER
236b8bee48 Final update to AES Major update to covert channel benchmarking 2020-11-20 10:53:10 +01:00
Guillume DIDIER
5eab981eec Major refactor that allows proper core selection
- covert / side channel are currently back in a non functional state
- two thread calibration however qorks and gets full experimental results
2020-10-22 14:38:41 +02:00
GuillaumeDIDIER
5cd3150a4b Add a draft module for AES attacks 2020-08-04 14:33:33 +02:00
GuillaumeDIDIER
144b4a498a Create and add cpuid crate 2020-05-27 14:00:19 +02:00
GuillaumeDIDIER
26b2d22942 Update result analysis scripts and code to the version for results-2020-04-20 2020-05-01 10:24:15 +02:00
Guillume DIDIER
bb8996efd0 Add analysis python script
This script currently just parses the CSV.
Future update should include plotting various metrics.
2020-04-13 11:16:46 +02:00
guillaume didier
2da2e7bf8e Rename cache utils 2020-02-05 10:23:52 +01:00
guillaume didier
6a0bd9b757 Start work on the cache info module 2019-12-22 15:24:21 +01:00
Guillaume DIDIER
33006a7db1 Untrack a temporary IDE file. 2019-10-21 13:16:04 +02:00
Guillaume DIDIER
e010900715 Test infrastructure
- serial port
- harnesses using qemu
2019-10-21 13:10:53 +02:00
Guillaume DIDIER
5a528f7508 Proper VGA driver, just missing print! / println! support. 2019-10-06 17:16:19 +02:00
Guillaume DIDIER
49d7c3e508 First bootable kernel 2019-10-02 09:52:19 +02:00
Guillaume DIDIER
7db6d00a42 Add CLion config files 2019-10-01 15:02:46 +02:00