9 Commits

Author	SHA1	Message	Date
Guillume DIDIER	3c8c00facb	Fix compile issue	2021-07-19 09:33:54 +02:00
Guillume DIDIER	78c4018a04	Document issues around number of handles per page / cache line ... The two channel used to have different invariants. Currently the enforcement of any limitation of handle per page or handle per cache line has been removed, hence document this issue in the code.	2021-07-19 09:17:09 +02:00
Guillume DIDIER	4cbacf96a9	Fix a bug in the improved Basic Timing Cache Channel calibration ... The cache line were not properly reset to Invalid state, which messe up F+R calibration. The Invalid state calibration is now done with a flush victim op, instead of a noop.	2021-07-19 09:15:20 +02:00
Guillume DIDIER	28f75075e3	Hotfix naive basic timing cache channel for use in prefetcher experiments	2021-07-19 09:01:24 +02:00
Guillume DIDIER	b7b5cbbfc3	Update the cache channel interface	2021-06-28 16:26:02 +02:00
Guillume DIDIER	e4c838e8b0	Rust nightly update - basic_timing_cache_channel ... Make sure this compiles with th newer nightly	2021-06-10 11:17:31 +02:00
Guillume DIDIER	68263dcd3a	New version of the benchmark program	2021-01-28 09:36:15 +01:00
Guillume DIDIER	7a5cae722c	New bersion of the side channels, with common implementation for F+R and F+F	2021-01-26 10:03:50 +01:00
Guillume DIDIER	a331fdd76e	Add a crate meant to one day factorize some common code to timing side channels	2020-10-22 14:49:09 +02:00