Start working on cache detection using Clementine Maurice's performance counter approach.
Add a new crate for that, getting out of cache_utils no_std / use_std mess.
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parent
a20210e5d7
commit
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4
Cargo.lock
generated
4
Cargo.lock
generated
@ -112,6 +112,10 @@ dependencies = [
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"nix 0.28.0",
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]
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[[package]]
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name = "cache_slice"
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version = "0.1.0"
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[[package]]
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name = "cache_utils"
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version = "0.1.0"
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@ -15,5 +15,6 @@ members = [
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"basic_timing_cache_channel",
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"turn_lock",
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"CacheObserver",
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"dendrobates-t-azureus"
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"dendrobates-t-azureus",
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"cache_slice",
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]
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6
cache_slice/Cargo.toml
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6
cache_slice/Cargo.toml
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@ -0,0 +1,6 @@
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[package]
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name = "cache_slice"
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version = "0.1.0"
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edition = "2021"
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[dependencies]
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24
cache_slice/src/bin/rdmsr.rs
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24
cache_slice/src/bin/rdmsr.rs
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@ -0,0 +1,24 @@
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use cache_slice::msr;
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use std::env;
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fn main() {
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let mut args = env::args().into_iter();
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args.next();
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for arg in args {
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match arg.parse::<u32>() {
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Ok(msr) => {
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match msr::read_msr_on_cpu(msr, 0) {
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Ok(result) => {
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println!("MSR {}: {:x}", msr, result);
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},
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Err(e) => {
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eprintln!("Error, failed to read MSR {}: {}", msr, e);
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}
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}
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},
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Err(e) => {
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eprintln!("Error: {}", e);
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eprintln!("{} is not a valid MSR number", arg);
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}
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}
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}
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}
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16
cache_slice/src/lib.rs
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16
cache_slice/src/lib.rs
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@ -0,0 +1,16 @@
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pub mod msr;
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pub fn add(left: u64, right: u64) -> u64 {
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left + right
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}
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#[cfg(test)]
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mod tests {
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use super::*;
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#[test]
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fn it_works() {
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let result = add(2, 2);
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assert_eq!(result, 4);
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}
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}
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42
cache_slice/src/msr.rs
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42
cache_slice/src/msr.rs
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@ -0,0 +1,42 @@
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use core::mem::size_of;
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use std::format;
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use std::fs::{File, OpenOptions};
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use std::os::unix::fs::FileExt;
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use std::io::{Result, Error, ErrorKind};
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pub fn write_msr_on_cpu(msr: u32, cpu: u8, value: u64) -> Result<()> {
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let path = format!("/dev/cpu/{}/msr", cpu);
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let file : File = OpenOptions::new().write(true).open(path).expect("Failed to open MSR, are you running as root ?");
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match file.write_at(&value.to_ne_bytes(), msr as u64) {
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Ok(size) => {
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if size == size_of::<u64>() {
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Ok(())
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} else {
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Err(Error::other("Failed to write complete value"))
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}
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},
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Err(e) => Err(e)
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}
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}
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pub fn read_msr_on_cpu(msr: u32, cpu: u8) -> Result<u64> {
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let path = format!("/dev/cpu/{}/msr", cpu);
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let file : File = OpenOptions::new().read(true).open(path).expect("Failed to open MSR, are you running as root ?");
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let mut read_data = [0u8; size_of::<u64>()];
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match file.read_at(&mut read_data, msr as u64) {
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Ok(size) => {
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if size == size_of::<u64>() {
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Ok(u64::from_ne_bytes(read_data))
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} else {
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Err(Error::other("Failed to write complete value"))
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}
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},
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Err(e) => Err(e)
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}
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}
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#[cfg(test)]
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mod tests {
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use super::*;
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// TODO how can we test model specific register read / write ?
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}
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