Change slice number type to u8 to avoid confusion
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a4e617021d
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@ -3,7 +3,7 @@
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use crate::complex_addressing::cache_slicing;
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use crate::complex_addressing::cache_slicing;
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use crate::{flush, maccess, rdtsc_fence};
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use crate::{flush, maccess, rdtsc_fence};
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use cpuid::MicroArchitecture;
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use cpuid::{CPUVendor, MicroArchitecture};
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use core::arch::x86_64 as arch_x86;
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use core::arch::x86_64 as arch_x86;
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#[cfg(feature = "no_std")]
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#[cfg(feature = "no_std")]
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@ -278,14 +278,24 @@ fn calibrate_impl_fixed_freq(
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let from_bucket = |bucket: usize| -> u64 { (bucket * hist_params.bucket_size) as u64 };
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let from_bucket = |bucket: usize| -> u64 { (bucket * hist_params.bucket_size) as u64 };
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let slicing = if let Some(uarch) = MicroArchitecture::get_micro_architecture() {
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let slicing = if let Some(uarch) = MicroArchitecture::get_micro_architecture() {
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Some(cache_slicing(uarch, 8))
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if let Some(vendor_family_model_stepping) = MicroArchitecture::get_family_model_stepping() {
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Some(cache_slicing(
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uarch,
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8,
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vendor_family_model_stepping.0,
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vendor_family_model_stepping.1,
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vendor_family_model_stepping.2,
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))
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} else {
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None
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}
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} else {
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} else {
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None
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None
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};
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};
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let h = if let Some(s) = slicing {
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let h = if let Some(s) = slicing {
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if s.can_hash() {
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if s.can_hash() {
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Some(|addr: usize| -> usize { slicing.unwrap().hash(addr).unwrap() })
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Some(|addr: usize| -> u8 { slicing.unwrap().hash(addr).unwrap() })
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} else {
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} else {
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None
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None
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}
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}
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@ -508,14 +518,24 @@ fn calibrate_fixed_freq_2_thread_impl<I: Iterator<Item = (usize, usize)>>(
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let from_bucket = |bucket: usize| -> u64 { (bucket * hist_params.bucket_size) as u64 };
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let from_bucket = |bucket: usize| -> u64 { (bucket * hist_params.bucket_size) as u64 };
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let slicing = if let Some(uarch) = MicroArchitecture::get_micro_architecture() {
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let slicing = if let Some(uarch) = MicroArchitecture::get_micro_architecture() {
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Some(cache_slicing(uarch, 8))
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if let Some(vendor_family_model_stepping) = MicroArchitecture::get_family_model_stepping() {
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Some(cache_slicing(
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uarch,
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8,
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vendor_family_model_stepping.0,
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vendor_family_model_stepping.1,
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vendor_family_model_stepping.2,
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))
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} else {
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None
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}
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} else {
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} else {
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None
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None
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};
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};
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let h = if let Some(s) = slicing {
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let h = if let Some(s) = slicing {
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if s.can_hash() {
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if s.can_hash() {
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Some(|addr: usize| -> usize { slicing.unwrap().hash(addr).unwrap() })
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Some(|addr: usize| -> u8 { slicing.unwrap().hash(addr).unwrap() })
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} else {
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} else {
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None
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None
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}
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}
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@ -1,13 +1,29 @@
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use crate::complex_addressing::CacheSlicing::{
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use crate::complex_addressing::CacheSlicing::{
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ComplexAddressing, NoSlice, SimpleAddressing, Unsupported,
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ComplexAddressing, NoSlice, SimpleAddressing, Unsupported,
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};
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};
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use cpuid::MicroArchitecture;
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use cpuid::{CPUVendor, MicroArchitecture};
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#[cfg(feature = "no_std")]
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use hashbrown::HashMap;
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#[cfg(feature = "no_std")]
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use hashbrown::HashSet;
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#[cfg(feature = "use_std")]
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use std::collections::HashMap;
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#[cfg(feature = "use_std")]
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use std::collections::HashSet;
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#[derive(Debug, Copy, Clone)]
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pub struct SimpleAddressingParams {
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pub shift: u8, // How many trailing zeros
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pub bits: u8, // How many ones
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}
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#[derive(Debug, Copy, Clone)]
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#[derive(Debug, Copy, Clone)]
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pub enum CacheSlicing {
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pub enum CacheSlicing {
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Unsupported,
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Unsupported,
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ComplexAddressing(&'static [usize]),
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ComplexAddressing(&'static [usize]),
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SimpleAddressing(usize),
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SimpleAddressing(SimpleAddressingParams),
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NoSlice,
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NoSlice,
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}
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}
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const SANDYBRIDGE_TO_SKYLAKE_FUNCTIONS: [usize; 4] = [
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const SANDYBRIDGE_TO_SKYLAKE_FUNCTIONS: [usize; 4] = [
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@ -16,47 +32,74 @@ const SANDYBRIDGE_TO_SKYLAKE_FUNCTIONS: [usize; 4] = [
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0b1111_0011_0011_0011_0010_0100_1100_0100_000000,
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0b1111_0011_0011_0011_0010_0100_1100_0100_000000,
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0b0, // TODO
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0b0, // TODO
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];
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];
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const KABYLAKE_i9_FUNCTIONS: [usize; 4] = [
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0b0000_1111_1111_1101_0101_1101_0101_0001_000000,
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0b0000_0110_1111_1011_1010_1100_0100_1000_000000,
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0b0000_1111_1110_0001_1111_1100_1011_0000_000000,
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0b0, // TODO
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];
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// missing functions for more than 8 cores.
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// missing functions for more than 8 cores.
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pub fn cache_slicing(uarch: MicroArchitecture, physical_cores: u8) -> CacheSlicing {
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// FIXME : Need to account for Family Model (and potentially stepping)
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// Amongst other thing Crystal well products have a different function. (0x6_46)
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// Same thing for Kaby Lake with 8 cores apparently.
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pub fn cache_slicing(
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uarch: MicroArchitecture,
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physical_cores: u8,
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vendor: CPUVendor,
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family_model_display: u32,
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stepping: u32,
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) -> CacheSlicing {
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let trailing_zeros = physical_cores.trailing_zeros();
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let trailing_zeros = physical_cores.trailing_zeros();
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if physical_cores != (1 << trailing_zeros) {
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if physical_cores != (1 << trailing_zeros) {
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return Unsupported;
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return Unsupported;
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}
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}
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match uarch {
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match uarch {
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MicroArchitecture::Skylake
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MicroArchitecture::Skylake | MicroArchitecture::CoffeeLake => {
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| MicroArchitecture::KabyLake
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| MicroArchitecture::CoffeeLake => {
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ComplexAddressing(&SANDYBRIDGE_TO_SKYLAKE_FUNCTIONS[0..((trailing_zeros + 1) as usize)])
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ComplexAddressing(&SANDYBRIDGE_TO_SKYLAKE_FUNCTIONS[0..((trailing_zeros + 1) as usize)])
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},
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}
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MicroArchitecture::KabyLake => {
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ComplexAddressing(&KABYLAKE_i9_FUNCTIONS[0..((trailing_zeros + 1) as usize)])
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}
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MicroArchitecture::SandyBridge
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MicroArchitecture::SandyBridge
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| MicroArchitecture::Haswell | MicroArchitecture::HaswellE
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| MicroArchitecture::HaswellE
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| MicroArchitecture::Broadwell
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| MicroArchitecture::Broadwell
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| MicroArchitecture::IvyBridge | MicroArchitecture::IvyBridgeE => {
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| MicroArchitecture::IvyBridge
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| MicroArchitecture::IvyBridgeE => {
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ComplexAddressing(&SANDYBRIDGE_TO_SKYLAKE_FUNCTIONS[0..((trailing_zeros) as usize)])
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ComplexAddressing(&SANDYBRIDGE_TO_SKYLAKE_FUNCTIONS[0..((trailing_zeros) as usize)])
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},
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}
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MicroArchitecture::Haswell => {
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if family_model_display == 0x06_46 {
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// Crystal Well
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Unsupported
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} else {
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ComplexAddressing(&SANDYBRIDGE_TO_SKYLAKE_FUNCTIONS[0..((trailing_zeros) as usize)])
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}
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}
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MicroArchitecture::Nehalem | MicroArchitecture::Westmere => {
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MicroArchitecture::Nehalem | MicroArchitecture::Westmere => {
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SimpleAddressing(((physical_cores -1) as usize) << 6 + 8)// Hardcoded for 4 cores FIXME !!!
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Unsupported //SimpleAddressing(((physical_cores - 1) as usize) << 6 + 8) // Hardcoded for 4 cores FIXME !!!
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}
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}
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_ => Unsupported,
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_ => Unsupported,
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}
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}
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}
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}
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fn hash(addr: usize, mask: usize) -> usize {
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fn hash(addr: usize, mask: usize) -> u8 {
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((addr & mask).count_ones() & 1) as usize
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((addr & mask).count_ones() & 1) as u8
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}
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}
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impl CacheSlicing {
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impl CacheSlicing {
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pub fn can_hash(&self) -> bool {
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pub fn can_hash(&self) -> bool {
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match self {
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match self {
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Unsupported | NoSlice => false,
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Unsupported | NoSlice | SimpleAddressing(_) => false,
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ComplexAddressing(_) | SimpleAddressing(_) => true,
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ComplexAddressing(_) => true,
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}
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}
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}
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}
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pub fn hash(&self, addr: usize) -> Option<usize> {
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pub fn hash(&self, addr: usize) -> Option<u8> {
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match self {
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match self {
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SimpleAddressing(mask) => Some(addr & *mask),
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SimpleAddressing(mask) => None, //Some(addr & *mask),
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ComplexAddressing(masks) => {
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ComplexAddressing(masks) => {
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let mut res = 0;
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let mut res = 0;
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for mask in *masks {
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for mask in *masks {
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@ -68,4 +111,12 @@ impl CacheSlicing {
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_ => None,
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_ => None,
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}
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}
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}
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}
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pub fn image(&self, mask: usize) -> Option<HashSet<usize>> {
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None
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}
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pub fn kernel_compl_basis(&self, mask: usize) -> Option<HashMap<usize, usize>> {
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None
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}
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}
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}
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