Rename prefetcher_reverse to CacheObserver

.idea/DendrobatesTinctoriusAzureus.iml

@@ -40,6 +40,7 @@
       <sourceFolder url="file://$MODULE_DIR$/turn_lock/src" isTestSource="false" />
       <sourceFolder url="file://$MODULE_DIR$/covert_channels_benchmark/src" isTestSource="false" />
       <sourceFolder url="file://$MODULE_DIR$/prefetcher_reverse/src" isTestSource="false" />
+      <sourceFolder url="file://$MODULE_DIR$/CacheObserver/src" isTestSource="false" />
       <excludeFolder url="file://$MODULE_DIR$/cache_info/target" />
       <excludeFolder url="file://$MODULE_DIR$/cache_utils/target" />
       <excludeFolder url="file://$MODULE_DIR$/kernel/target" />

CacheObserver/Cargo.toml

@@ -1,5 +1,5 @@
 [package]
-name = "prefetcher_reverse"
+name = "CacheObserver"
 version = "0.1.0"
 authors = ["Guillaume DIDIER <guillaume.didier.2014@polytechnique.org>"]
 edition = "2018"

CacheObserver/Readme.md

@@ -4,7 +4,7 @@ CacheObserver - monitor what happens in the cache when doing memory accesses
 This framework, derived from https://github.com/MIAOUS-group/calibration-done-right,
 is built to help reverse engineer prefetchers on Intel CPUs.
 
-The main entry point of the framework is the `prefetcher_reverse` crate.
+The main entry point of the framework is the `CacheObserver` crate.
 
 The code presented runs under Fedora 30, and can also be made to run on Ubuntu 18.04 LTS with minor tweaks
 
@@ -22,7 +22,7 @@ non-boosted frequency.
 One can run all the experiments with the following instructions :
 
 ```
-cd prefetcher_reverse
+cd CacheObserver
 mkdir results-xxx
 cd results-xxx
 sudo ../setup.sh

CacheObserver/run-msr-bonus.sh

@@ -0,0 +1,8 @@
+#!/bin/bash
+PREFETCH_MSR=$1
+sudo wrmsr -a 0x1a4 $PREFETCH_MSR
+sudo echo wrmsr -a 0x1a4 $PREFETCH_MSR
+sudo rdmsr -a 0x1a4
+cargo run --release --bin bonus_access_pattern > bonusap-with-${PREFETCH_MSR}-prefetcher.log
+sudo rdmsr -a 0x1a4
+

CacheObserver/run-msr-extrap.sh

@@ -0,0 +1,8 @@
+#!/bin/bash
+PREFETCH_MSR=$1
+sudo wrmsr -a 0x1a4 $PREFETCH_MSR
+sudo echo wrmsr -a 0x1a4 $PREFETCH_MSR
+sudo rdmsr -a 0x1a4
+cargo run --release --bin extra_access_pattern > extrap-with-${PREFETCH_MSR}-prefetcher.log
+sudo rdmsr -a 0x1a4
+

CacheObserver/run-msr.sh

@@ -2,6 +2,6 @@
 PREFETCH_MSR=$1
 sudo wrmsr -a 0x1a4 $PREFETCH_MSR
 sudo rdmsr -a 0x1a4
-cargo run --bin prefetcher_reverse --release > with-${PREFETCH_MSR}-prefetcher.log
+cargo run --bin CacheObserver --release > with-${PREFETCH_MSR}-prefetcher.log
 
 

CacheObserver/src/bin/all_experiments.rs

@@ -14,7 +14,7 @@ Alternatively, limit to 3 accesses ?
 use cache_utils::ip_tool::{Function, TIMED_MACCESS};
 use itertools::Itertools;
 use nix::sched::sched_yield;
-use prefetcher_reverse::{
+use CacheObserver::{
     pattern_helper, FullPageDualProbeResults, PatternAccess, Prober, PAGE_CACHELINE_LEN,
 };
 
@@ -160,36 +160,28 @@ fn main() {
         unique_ip: true,
     };
 
-    let mut experiments: Vec<(String, usize, usize, Box<dyn Fn(usize, usize) -> Vec<usize>>)> = vec![];
+    let mut experiments: Vec<(
-    for class in [
+        String,
-        (
+        usize,
+        usize,
+        Box<dyn Fn(usize, usize) -> Vec<usize>>,
+    )> = vec![];
+    for class in [(
         "",
         Box::new(|k: usize| {
-
             let f = Box::new(move |i, j| {
-                    let mut v = vec![
+                let mut v = vec![i, j];
-                        i,j,
-                    ];
                 v.truncate(k);
                 v
             }) as Box<dyn Fn(usize, usize) -> Vec<usize>>;
-                let i_limit = if k > 0 {
+            let i_limit = if k > 0 { PAGE_CACHELINE_LEN } else { 1 };
-                    PAGE_CACHELINE_LEN
+            let j_limit = if k > 1 { PAGE_CACHELINE_LEN } else { 1 };
-                } else {
+            (i_limit, j_limit, f)
-                    1
-                };
-                let j_limit = if k > 1 {
-                    PAGE_CACHELINE_LEN
-                } else {
-                    1
-                };
-                (i_limit,j_limit,f)
         }) as Box<dyn Fn(usize) -> (usize, usize, Box<dyn Fn(usize, usize) -> Vec<usize>>)>,
-        ),
+    )] {
-    ] {
+        for k in [0, 1, 2] {
-        for k in [0,1,2] {
             let exp = class.1(k);
-            experiments.push((format!("{}{}", class.0, k),exp.0, exp.1, exp.2));
+            experiments.push((format!("{}{}", class.0, k), exp.0, exp.1, exp.2));
         }
     }
 
@@ -224,7 +216,12 @@ fn main() {
         ),
     ] {
         for k in [1, 2, 3, 4, 8] {
-            experiments.push((format!("{}{}", class.0, k), PAGE_CACHELINE_LEN, PAGE_CACHELINE_LEN, class.1(k)));
+            experiments.push((
+                format!("{}{}", class.0, k),
+                PAGE_CACHELINE_LEN,
+                PAGE_CACHELINE_LEN,
+                class.1(k),
+            ));
         }
     }
 
@@ -241,29 +238,36 @@ fn main() {
         }) as Box<dyn Fn(usize) -> Box<dyn Fn(usize, usize) -> Vec<usize>>>,
     )] {
         for len in [2, 3, 4] {
-            experiments.push((format!("{}{}", class.0, len), PAGE_CACHELINE_LEN, PAGE_CACHELINE_LEN, class.1(len)));
+            experiments.push((
+                format!("{}{}", class.0, len),
+                PAGE_CACHELINE_LEN,
+                PAGE_CACHELINE_LEN,
+                class.1(len),
+            ));
         }
     }
 
-    for class in [
+    for class in [(
-        (
         "F",
         Box::new(|k: isize| {
             Box::new(move |i, j| {
                 vec![
                     i,
-                        (i as isize + k + PAGE_CACHELINE_LEN as isize) as usize
+                    (i as isize + k + PAGE_CACHELINE_LEN as isize) as usize % PAGE_CACHELINE_LEN,
-                            % PAGE_CACHELINE_LEN,
                     j,
                     (i as isize + 2 * k + PAGE_CACHELINE_LEN as isize) as usize
                         % PAGE_CACHELINE_LEN,
                 ]
             }) as Box<dyn Fn(usize, usize) -> Vec<usize>>
         }) as Box<dyn Fn(isize) -> Box<dyn Fn(usize, usize) -> Vec<usize>>>,
-        ),
+    )] {
-    ] {
         for k in [4 as isize, 3, 2, 1, -1, -2, -3, -4] {
-            experiments.push((format!("{}{}", class.0, k), PAGE_CACHELINE_LEN, PAGE_CACHELINE_LEN, class.1(k)));
+            experiments.push((
+                format!("{}{}", class.0, k),
+                PAGE_CACHELINE_LEN,
+                PAGE_CACHELINE_LEN,
+                class.1(k),
+            ));
         }
     }
 

CacheObserver/src/bin/bonus_access_pattern.rs

@@ -14,7 +14,7 @@ Alternatively, limit to 3 accesses ?
 use cache_utils::ip_tool::{Function, TIMED_MACCESS};
 use itertools::Itertools;
 use nix::sched::sched_yield;
-use prefetcher_reverse::{
+use CacheObserver::{
     pattern_helper, FullPageDualProbeResults, PatternAccess, Prober, PAGE_CACHELINE_LEN,
 };
 

CacheObserver/src/bin/exhaustive_access_pattern.rs

@@ -14,7 +14,7 @@ Alternatively, limit to 3 accesses ?
 use cache_utils::ip_tool::{Function, TIMED_MACCESS};
 use itertools::Itertools;
 use nix::sched::sched_yield;
-use prefetcher_reverse::{
+use CacheObserver::{
     pattern_helper, FullPageDualProbeResults, PatternAccess, Prober, PAGE_CACHELINE_LEN,
 };
 

CacheObserver/src/bin/extra_access_pattern.rs

@@ -14,7 +14,7 @@ Alternatively, limit to 3 accesses ?
 use cache_utils::ip_tool::{Function, TIMED_MACCESS};
 use itertools::Itertools;
 use nix::sched::sched_yield;
-use prefetcher_reverse::{
+use CacheObserver::{
     pattern_helper, FullPageDualProbeResults, PatternAccess, Prober, PAGE_CACHELINE_LEN,
 };
 

CacheObserver/src/bin/naive_flush_flush.rs

@@ -8,7 +8,7 @@ use cache_utils::calibration::{Threshold, PAGE_LEN};
 use cache_utils::maccess;
 use cache_utils::mmap::MMappedMemory;
 use flush_flush::naive::NaiveFlushAndFlush;
-use prefetcher_reverse::CACHE_LINE_LEN;
+use CacheObserver::CACHE_LINE_LEN;
 
 const ITERATIONS: i32 = 128;
 const THRESHOLD: usize = 175; // For Cyber Cobaye

CacheObserver/src/bin/new_page.rs

@@ -1,5 +1,5 @@
 use cache_utils::ip_tool::{Function, TIMED_MACCESS};
-use prefetcher_reverse::{pattern_helper, Prober, PAGE_CACHELINE_LEN};
+use CacheObserver::{pattern_helper, Prober, PAGE_CACHELINE_LEN};
 
 pub const NUM_ITERATION: usize = 1 << 10;
 

CacheObserver/src/bin/rpa_patterns.rs

@@ -11,12 +11,12 @@ use cache_utils::mmap;
 use cache_utils::mmap::MMappedMemory;
 use flush_flush::{FFHandle, FFPrimitives, FlushAndFlush};
 use nix::Error;
-use prefetcher_reverse::{
-    pattern_helper, reference_patterns, Prober, CACHE_LINE_LEN, PAGE_CACHELINE_LEN,
-};
 use rand::seq::SliceRandom;
 use std::iter::Cycle;
 use std::ops::Range;
+use CacheObserver::{
+    pattern_helper, reference_patterns, Prober, CACHE_LINE_LEN, PAGE_CACHELINE_LEN,
+};
 
 pub const NUM_ITERATION: usize = 1 << 10;
 pub const NUM_PAGES: usize = 256;

CacheObserver/src/bin/stream.rs

@@ -1,7 +1,7 @@
 use cache_utils::ip_tool::{Function, TIMED_MACCESS};
 use cache_utils::{flush, maccess};
-use prefetcher_reverse::{pattern_helper, Prober, PAGE_CACHELINE_LEN};
 use std::arch::x86_64 as arch_x86;
+use CacheObserver::{pattern_helper, Prober, PAGE_CACHELINE_LEN};
 
 pub const NUM_ITERATION: usize = 1 << 10;
 

CacheObserver/src/bin/strides.rs

@@ -1,5 +1,5 @@
 use cache_utils::ip_tool::{Function, TIMED_MACCESS};
-use prefetcher_reverse::{pattern_helper, Prober, PAGE_CACHELINE_LEN};
+use CacheObserver::{pattern_helper, Prober, PAGE_CACHELINE_LEN};
 
 pub const NUM_ITERATION: usize = 1 << 10;
 

CacheObserver/src/main.rs

@@ -11,11 +11,9 @@ use cache_utils::mmap;
 use cache_utils::mmap::MMappedMemory;
 use flush_flush::{FFHandle, FFPrimitives, FlushAndFlush};
 use nix::Error;
-use prefetcher_reverse::{
-    pattern_helper, PatternAccess, Prober, CACHE_LINE_LEN, PAGE_CACHELINE_LEN,
-};
 use rand::seq::SliceRandom;
 use std::iter::Cycle;
+use CacheObserver::{pattern_helper, PatternAccess, Prober, CACHE_LINE_LEN, PAGE_CACHELINE_LEN};
 
 pub const NUM_ITERATION: usize = 1 << 10;
 pub const NUM_PAGES: usize = 256;

Cargo.lock

@@ -2,6 +2,22 @@
 # It is not intended for manual editing.
 version = 3
 
+[[package]]
+name = "CacheObserver"
+version = "0.1.0"
+dependencies = [
+ "basic_timing_cache_channel",
+ "bitvec",
+ "cache_side_channel",
+ "cache_utils",
+ "flush_flush",
+ "flush_reload",
+ "itertools",
+ "lazy_static",
+ "nix",
+ "rand",
+]
+
 [[package]]
 name = "aes-t-tables"
 version = "0.1.0"
@@ -366,22 +382,6 @@ version = "0.2.10"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "ac74c624d6b2d21f425f752262f42188365d7b8ff1aff74c82e45136510a4857"
 
-[[package]]
-name = "prefetcher_reverse"
-version = "0.1.0"
-dependencies = [
- "basic_timing_cache_channel",
- "bitvec",
- "cache_side_channel",
- "cache_utils",
- "flush_flush",
- "flush_reload",
- "itertools",
- "lazy_static",
- "nix",
- "rand",
-]
-
 [[package]]
 name = "radium"
 version = "0.6.2"

Cargo.toml

@@ -13,7 +13,7 @@ members = [
     "flush_flush",
     "basic_timing_cache_channel",
     "turn_lock",
-    "prefetcher_reverse",
+    "CacheObserver",
 ]
 
 [package]