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Fixes around cacheline length magic number

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Cache line length is now a constant. This should eventually be replaced with some sort of lazy static info, that is extracted from CPUID if possible.
This commit is contained in:
Guillume DIDIER 2021-09-28 08:55:12 +02:00
parent d6c387b0d0
commit 6f8ae88e58
4 changed files with 16 additions and 12 deletions
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8
basic_timing_cache_channel/src/lib.rs
View File

@ -40,6 +40,8 @@ use std::ptr::slice_from_raw_parts;
pub mod naive; pub mod naive;
const CACHE_LINE_LENGTH: usize = 64; // FIXME MAGIC to be autodetected.
pub trait TimingChannelPrimitives: Debug + Send + Sync + Default { pub trait TimingChannelPrimitives: Debug + Send + Sync + Default {
unsafe fn attack(&self, addr: *const u8) -> u64; unsafe fn attack(&self, addr: *const u8) -> u64;
const NEED_RESET: bool; const NEED_RESET: bool;
@ -86,7 +88,7 @@ unsafe impl<T: TimingChannelPrimitives + Sync> Sync for TopologyAwareTimingChann
impl<T: TimingChannelPrimitives> TopologyAwareTimingChannel<T> { impl<T: TimingChannelPrimitives> TopologyAwareTimingChannel<T> {
pub fn new(main_core: usize, helper_core: usize) -> Result<Self, TopologyAwareError> { pub fn new(main_core: usize, helper_core: usize) -> Result<Self, TopologyAwareError> {
if let Some(slicing) = get_cache_attack_slicing(find_core_per_socket()) { if let Some(slicing) = get_cache_attack_slicing(find_core_per_socket(), CACHE_LINE_LENGTH) {
let ret = Self { let ret = Self {
thresholds: Default::default(), thresholds: Default::default(),
addresses: Default::default(), addresses: Default::default(),
@ -135,7 +137,7 @@ impl<T: TimingChannelPrimitives> TopologyAwareTimingChannel<T> {
let mut calibrate_results2t_vec = Vec::new(); let mut calibrate_results2t_vec = Vec::new();
let slicing = match get_cache_attack_slicing(core_per_socket) { let slicing = match get_cache_attack_slicing(core_per_socket, CACHE_LINE_LENGTH) {
Some(s) => s, Some(s) => s,
None => { None => {
return Err(TopologyAwareError::NoSlicing); return Err(TopologyAwareError::NoSlicing);
@ -148,7 +150,7 @@ impl<T: TimingChannelPrimitives> TopologyAwareTimingChannel<T> {
let mut r = unsafe { let mut r = unsafe {
calibrate_fixed_freq_2_thread( calibrate_fixed_freq_2_thread(
&page[0] as *const u8, &page[0] as *const u8,
64, CACHE_LINE_LENGTH,
page.len() as isize, page.len() as isize,
&mut core_pairs.clone(), &mut core_pairs.clone(),
&operations, &operations,

11
cache_utils/src/bin/two_thread_cal.rs
View File

@ -2,11 +2,10 @@
use cache_utils::calibration::{ use cache_utils::calibration::{
accumulate, calibrate_fixed_freq_2_thread, calibration_result_to_ASVP, flush_and_reload, accumulate, calibrate_fixed_freq_2_thread, calibration_result_to_ASVP, flush_and_reload,
get_cache_attack_slicing, get_cache_slicing, load_and_flush, map_values, only_flush, get_cache_attack_slicing, load_and_flush, map_values, only_flush, only_reload, reduce,
only_reload, reduce, reload_and_flush, CalibrateOperation2T, CalibrateResult2T, reload_and_flush, CalibrateOperation2T, CalibrateResult2T, CalibrationOptions, ErrorPrediction,
CalibrationOptions, ErrorPrediction, ErrorPredictions, HistParams, HistogramCumSum, ErrorPredictions, HistParams, HistogramCumSum, PotentialThresholds, ThresholdError, Verbosity,
PotentialThresholds, ThresholdError, Verbosity, ASP, ASVP, AV, CFLUSH_BUCKET_NUMBER, ASP, ASVP, AV, CFLUSH_BUCKET_NUMBER, CFLUSH_BUCKET_SIZE, CFLUSH_NUM_ITER, SP, SVP,
CFLUSH_BUCKET_SIZE, CFLUSH_NUM_ITER, SP, SVP,
}; };
use cache_utils::mmap::MMappedMemory; use cache_utils::mmap::MMappedMemory;
use cache_utils::{flush, maccess, noop}; use cache_utils::{flush, maccess, noop};
@ -245,7 +244,7 @@ fn main() {
.position(|op| op.name == hit_name) .position(|op| op.name == hit_name)
.unwrap(); .unwrap();
let slicing = get_cache_attack_slicing(core_per_socket); let slicing = get_cache_attack_slicing(core_per_socket, cache_line_size);
let h = if let Some(s) = slicing { let h = if let Some(s) = slicing {
|addr: usize| -> usize { slicing.unwrap().hash(addr) } |addr: usize| -> usize { slicing.unwrap().hash(addr) }

2
cache_utils/src/calibrate_2t.rs
View File

@ -88,7 +88,7 @@ fn calibrate_fixed_freq_2_thread_impl<I: Iterator<Item = (usize, usize)>, T>(
let to_bucket = |time: u64| -> usize { time as usize / bucket_size }; let to_bucket = |time: u64| -> usize { time as usize / bucket_size };
let from_bucket = |bucket: usize| -> u64 { (bucket * bucket_size) as u64 }; let from_bucket = |bucket: usize| -> u64 { (bucket * bucket_size) as u64 };
let slicing = get_cache_attack_slicing(core_per_socket).unwrap(); let slicing = get_cache_attack_slicing(core_per_socket, cache_line_length).unwrap();
let mut ret = Vec::new(); let mut ret = Vec::new();

7
cache_utils/src/calibration.rs
View File

@ -488,7 +488,10 @@ fn get_cache_slicing(core_per_socket: u8) -> Option<CacheSlicing> {
} }
} }
pub fn get_cache_attack_slicing(core_per_socket: u8) -> Option<CacheAttackSlicing> { pub fn get_cache_attack_slicing(
core_per_socket: u8,
cache_line_length: usize,
) -> Option<CacheAttackSlicing> {
if let Some(uarch) = MicroArchitecture::get_micro_architecture() { if let Some(uarch) = MicroArchitecture::get_micro_architecture() {
if let Some(vendor_family_model_stepping) = MicroArchitecture::get_family_model_stepping() { if let Some(vendor_family_model_stepping) = MicroArchitecture::get_family_model_stepping() {
Some(CacheAttackSlicing::from( Some(CacheAttackSlicing::from(
@ -499,7 +502,7 @@ pub fn get_cache_attack_slicing(core_per_socket: u8) -> Option<CacheAttackSlicin
vendor_family_model_stepping.1, vendor_family_model_stepping.1,
vendor_family_model_stepping.2, vendor_family_model_stepping.2,
), ),
64, cache_line_length,
)) // FIXME Cache length magic number )) // FIXME Cache length magic number
} else { } else {
None None