Start working on prefetcher reverse engineering experiment

.idea/DendrobatesTinctoriusAzureus.iml

@@ -39,6 +39,7 @@
       <sourceFolder url="file://$MODULE_DIR$/basic_timing_cache_channel/src" isTestSource="false" />
       <sourceFolder url="file://$MODULE_DIR$/turn_lock/src" isTestSource="false" />
       <sourceFolder url="file://$MODULE_DIR$/covert_channels_benchmark/src" isTestSource="false" />
+      <sourceFolder url="file://$MODULE_DIR$/prefetcher_reverse/src" isTestSource="false" />
       <excludeFolder url="file://$MODULE_DIR$/cache_info/target" />
       <excludeFolder url="file://$MODULE_DIR$/cache_utils/target" />
       <excludeFolder url="file://$MODULE_DIR$/kernel/target" />

Cargo.lock

@@ -335,6 +335,13 @@ version = "0.2.9"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "c36fa947111f5c62a733b652544dd0016a43ce89619538a8ef92724a6f501a20"
 
+[[package]]
+name = "prefetcher_reverse"
+version = "0.1.0"
+dependencies = [
+ "cache_utils",
+]
+
 [[package]]
 name = "rand"
 version = "0.7.3"

Cargo.toml

@@ -13,6 +13,7 @@ members = [
     "flush_flush",
     "basic_timing_cache_channel",
     "turn_lock",
+    "prefetcher_reverse",
 ]
 
 [package]

prefetcher_reverse/.cargo/config

@@ -0,0 +1,2 @@
+[build]
+target = "x86_64-unknown-linux-gnu"

prefetcher_reverse/Cargo.toml

@@ -0,0 +1,10 @@
+[package]
+name = "prefetcher_reverse"
+version = "0.1.0"
+authors = ["Guillume DIDIER <guillaume.didier@inria.fr>"]
+edition = "2018"
+
+# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
+
+[dependencies]
+cache_utils = { path = "../cache_utils"}

prefetcher_reverse/src/main.rs

@@ -0,0 +1,40 @@
+use cache_utils::calibration::PAGE_LEN;
+
+pub const CACHE_LINE_LEN: usize = 64;
+
+fn max_stride(len: usize) -> isize {
+    if len == 0 {
+        1
+    } else {
+        (PAGE_LEN / (len * CACHE_LINE_LEN)) as isize
+    }
+}
+
+fn generate_pattern(len: usize, stride: isize) -> Vec<isize> {
+    if (stride * len as isize * CACHE_LINE_LEN as isize).abs() as usize > PAGE_LEN {
+        panic!("This is illegal");
+    }
+    let mut res = Vec::with_capacity(len);
+    for i in 0..len {
+        res.push(i as isize * stride * CACHE_LINE_LEN as isize);
+    }
+    res
+}
+
+fn main() {
+    /*
+    TODO List :
+    Calibration & core selection (select one or two cores with optimal error)
+    Then allocate a bunch of pages, and do accesses on each of them.
+
+    (Let's start with stride patterns : for len in 0..16, and then for stride in 1..maxs_stride(len), generate a vac of addresses and get the victim to execute, then dump all the page)
+
+     */
+
+    println!("Hello, world!");
+    println!("{:?}", generate_pattern(5, 2));
+    println!("{:?}", generate_pattern(5, 1));
+    println!("{:?}", generate_pattern(0, 1));
+    println!("{:?}", generate_pattern(5, 5));
+    println!("{:?}", generate_pattern(16, 16));
+}