Add missing files

aes-t-tables/prefetcher_notes

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+Core 2 :
+  MSR 0x1A0 [9] HW prfetcher disable
+  MSR 0x1A0 [19] Adjacent Cache line HW prfetcher disable
+  MSR 0x1A0 [37] DCU HW prfetcher disable
+  MSR 0x1A0 [39] IP HW prfetcher disable
+
+Sandy Bridge
+  MSR 0x1A4 (420) [0,1,2,3] various prefetcher disable
+

aes-t-tables/setup.sh

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+# For citron vert or Cyber cobaye - run with sudo
+# disable prefetchers
+wrmsr -a 420 15
+
+# performance cpu frequency governor
+cpupower frequency-set -g performance
+
+# No Turbo Boost
+echo 1 > /sys/devices/system/cpu/intel_pstate/no_turbo

aes-t-tables/src/naive_flush_and_reload.rs

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+use crate::{CacheStatus, ChannelFatalError, SideChannelError, SingleAddrCacheSideChannel};
+use cache_utils::calibration::only_reload;
+use cache_utils::flush;
+
+#[derive(Debug)]
+pub struct NaiveFlushAndReload {
+    pub threshold: u64,
+    current: Option<*const u8>,
+}
+
+impl NaiveFlushAndReload {
+    pub fn from_threshold(threshold: u64) -> Self {
+        NaiveFlushAndReload {
+            threshold,
+            current: None,
+        }
+    }
+}
+
+impl SingleAddrCacheSideChannel for NaiveFlushAndReload {
+    fn test_single(&mut self, addr: *const u8) -> Result<CacheStatus, SideChannelError> {
+        if self.current != Some(addr) {
+            panic!(); // FIXME
+        }
+        let t = unsafe { only_reload(addr) };
+        if t > self.threshold {
+            Ok(CacheStatus::Miss)
+        } else {
+            Ok(CacheStatus::Hit)
+        }
+    }
+
+    fn prepare_single(&mut self, addr: *const u8) -> Result<(), SideChannelError> {
+        unsafe { flush(addr) };
+        self.current = Some(addr);
+        Ok(())
+    }
+
+    fn victim_single(&mut self, operation: &dyn Fn()) {
+        operation()
+    }
+
+    fn calibrate_single(
+        &mut self,
+        _addresses: impl IntoIterator<Item = *const u8>,
+    ) -> Result<(), ChannelFatalError> {
+        Ok(())
+    }
+}