242 lines
8.1 KiB
Rust
242 lines
8.1 KiB
Rust
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use raw_cpuid::CpuId;
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use crate::arch::CpuClass::{IntelCore, IntelXeon, IntelXeonSP};
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pub(crate) enum CpuClass {
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IntelCore,
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IntelXeon,
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IntelXeonSP,
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// Add further CPUs later on
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}
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pub(crate) fn determine_cpu_class() -> Option<CpuClass> {
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let cpuid = CpuId::new();
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let info = if let Some(info) = cpuid.get_feature_info() {
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info
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} else {
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return None;
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};
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// Todo, sift through the documentation to add support for more CPUs
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match (info.family_id(), info.model_id()) {
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(0x06, 0x4f)
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| (0x06, 0x2d)
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| (0x06, 0x3e)
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| (06, 0x3f)
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| (0x06, 0x56) => {
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Some(IntelXeon)
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}
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(0x06, 0x55) => {
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Some(IntelXeonSP)
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}
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// 42, 58, 60, 69, 70, 61, 71, 78, 94, 142, 158
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(0x06, 0x2a)
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| (0x06, 0x3a)
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| (0x06, 0x3c)
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| (0x06, 0x45)
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| (0x06, 0x46)
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| (0x06, 0x3d)
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| (0x06, 0x47)
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| (0x06, 0x4e)
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| (0x06, 0x5e)
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| (0x06, 0x8e)
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| (0x06, 0x9e) => {
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Some(IntelCore)
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}
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_ => {
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None
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}
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}
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}
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pub(crate) fn get_performance_counters_xeon() -> Option<&'static XeonPerfCounters> {
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let cpuid = CpuId::new();
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let info = if let Some(info) = cpuid.get_feature_info() {
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info
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} else {
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return None;
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};
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if info.family_id() != 6 {
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return None;
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}
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match info.model_id() {
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0x2d /* 45 */ => Some(&SANDY_BRIDGE_XEON),
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0x3e /* 62 */ => Some(&IVY_BRIDGE_XEON),
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0x3f /* 63 */ => Some(&HASWELL_XEON),
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0x56 /* 86 */ => Some(&BROADWELL_XEON),
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_ => None,
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}
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}
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pub(crate) fn get_performance_counters_core() -> Option<&'static CorePerfCounters> {
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let cpuid = CpuId::new();
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let info = if let Some(info) = cpuid.get_feature_info() {
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info
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} else {
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return None;
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};
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if info.family_id() != 6 {
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return None;
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}
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// TODO, review if the list can be extended to further CPUs
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// TODO, add post Cannon Lake stuff
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match info.model_id() {
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0x2a
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| 0x3a
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| 0x3c
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| 0x45
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| 0x46
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| 0x3d
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| 0x47 => Some(&SANDYBRIDGE_TO_BROADWELL_CORE),
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0x4e
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| 0x5e
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| 0x8e
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| 0x9e => Some(&SKYLAKE_KABYLAKE_CORE),
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_ => None,
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}
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}
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pub struct XeonPerfCounters {
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pub max_slice: u16,
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pub msr_pmon_ctr0: &'static [u64],
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pub msr_pmon_box_filter: &'static [u64],
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pub msr_pmon_ctl0: &'static [u64],
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pub msr_pmon_box_ctl: &'static [u64],
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pub val_box_freeze: u64,
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pub val_box_reset: u64,
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pub val_enable_counting: u64,
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pub val_select_event: u64,
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pub val_filter: u64,
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pub val_box_unfreeze: u64,
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}
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pub struct CorePerfCounters {
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pub max_slice: u16,
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pub msr_unc_perf_global_ctr: u64,
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pub val_enable_ctrs: u64,
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pub msr_unc_cbo_perfevtsel0: &'static [u64],
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pub msr_unc_cbo_per_ctr0: &'static [u64],
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pub val_disable_ctrs: u64,
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pub val_select_evt_core: u64,
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pub val_reset_ctrs: u64,
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}
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const SANDY_BRIDGE_XEON: XeonPerfCounters = XeonPerfCounters {
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max_slice: 8,
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msr_pmon_ctr0: &[0xd16, 0xd36, 0xd56, 0xd76,
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0xd96, 0xdb6, 0xdd6, 0xdf6],
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msr_pmon_box_filter: &[0xd14, 0xd34, 0xd54, 0xd74, 0xd94, 0xdb4, 0xdd4, 0xdf4],
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msr_pmon_ctl0: &[0xd10, 0xd30, 0xd50, 0xd70,
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0xd90, 0xdb0, 0xdd0, 0xdf0],
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msr_pmon_box_ctl: &[0xd04, 0xd24, 0xd44, 0xd64, 0xd84, 0xda4, 0xdc4, 0xde4],
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val_box_freeze: 0x10100,
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val_box_reset: 0x10103,
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val_enable_counting: 0x400000,
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val_select_event: 0x401134,
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val_filter: 0x7c0000,
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val_box_unfreeze: 0x10000,
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};
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const IVY_BRIDGE_XEON: XeonPerfCounters = XeonPerfCounters {
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max_slice: 15,
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msr_pmon_ctr0: &[0xd16, 0xd36, 0xd56, 0xd76, 0xd96, 0xdb6, 0xdd6, 0xdf6,
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0xe16, 0xe36, 0xe56, 0xe76, 0xe96, 0xeb6, 0xed6],
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msr_pmon_box_filter: &[0xd14, 0xd34, 0xd54, 0xd74, 0xd94, 0xdb4, 0xdd4, 0xdf4,
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0xe14, 0xe34, 0xe54, 0xe74, 0xe94, 0xeb4, 0xed4],
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msr_pmon_ctl0: &[0xd10, 0xd30, 0xd50, 0xd70, 0xd90, 0xdb0, 0xdd0, 0xdf0,
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0xe10, 0xe30, 0xe50, 0xe70, 0xe90, 0xeb0, 0xed0],
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msr_pmon_box_ctl: &[0xd04, 0xd24, 0xd44, 0xd64, 0xd84, 0xda4, 0xdc4, 0xde4,
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0xe04, 0xe24, 0xe44, 0xe64, 0xe84, 0xea4, 0xec4],
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val_box_freeze: 0x30100,
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val_box_reset: 0x30103,
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val_enable_counting: 0x400000,
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val_select_event: 0x401134,
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val_filter: 0x7e0010,
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val_box_unfreeze: 0x30000,
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};
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const HASWELL_XEON: XeonPerfCounters = XeonPerfCounters {
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max_slice: 18,
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msr_pmon_ctr0: &[0xe08, 0xe18, 0xe28, 0xe38, 0xe48, 0xe58, 0xe68, 0xe78, 0xe88,
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0xe98, 0xea8, 0xeb8, 0xec8, 0xed8, 0xee8, 0xef8, 0xf08, 0xf18],
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msr_pmon_box_filter: &[0xe05, 0xe15, 0xe25, 0xe35, 0xe45, 0xe55, 0xe65, 0xe75, 0xe85,
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0xe95, 0xea5, 0xeb5, 0xec5, 0xed5, 0xee5, 0xef5, 0xf05, 0xf15],
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msr_pmon_ctl0: &[0xe01, 0xe11, 0xe21, 0xe31, 0xe41, 0xe51, 0xe61, 0xe71, 0xe81,
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0xe91, 0xea1, 0xeb1, 0xec1, 0xed1, 0xee1, 0xef1, 0xf01, 0xf11],
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msr_pmon_box_ctl: &[0xe00, 0xe10, 0xe20, 0xe30, 0xe40, 0xe50, 0xe60, 0xe70, 0xe80,
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0xe90, 0xea0, 0xeb0, 0xec0, 0xed0, 0xee0, 0xef0, 0xf00, 0xf10],
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val_box_freeze: 0x30100,
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val_box_reset: 0x30103,
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val_enable_counting: 0x400000,
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val_select_event: 0x401134,
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val_filter: 0x7e0020,
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val_box_unfreeze: 0x30000,
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};
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const BROADWELL_XEON: XeonPerfCounters = XeonPerfCounters {
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max_slice: 24,
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msr_pmon_ctr0: &[0xe08, 0xe18, 0xe28, 0xe38, 0xe48, 0xe58, 0xe68, 0xe78,
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0xe88, 0xe98, 0xea8, 0xeb8, 0xec8, 0xed8, 0xee8, 0xef8,
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0xf08, 0xf18, 0xf28, 0xf38, 0xf48, 0xf58, 0xf68, 0xf78],
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msr_pmon_box_filter: &[0xe05, 0xe15, 0xe25, 0xe35, 0xe45, 0xe55, 0xe65, 0xe75,
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0xe85, 0xe95, 0xea5, 0xeb5, 0xec5, 0xed5, 0xee5, 0xef5,
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0xf05, 0xf15, 0xf25, 0xf35, 0xf45, 0xf55, 0xf65, 0xf75],
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msr_pmon_ctl0: &[0xe01, 0xe11, 0xe21, 0xe31, 0xe41, 0xe51, 0xe61, 0xe71,
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0xe81, 0xe91, 0xea1, 0xeb1, 0xec1, 0xed1, 0xee1, 0xef1,
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0xf01, 0xf11, 0xf21, 0xf31, 0xf41, 0xf51, 0xf61, 0xf71],
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msr_pmon_box_ctl: &[0xe00, 0xe10, 0xe20, 0xe30, 0xe40, 0xe50, 0xe60, 0xe70,
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0xe80, 0xe90, 0xea0, 0xeb0, 0xec0, 0xed0, 0xee0, 0xef0,
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0xf00, 0xf10, 0xf20, 0xf30, 0xf40, 0xf50, 0xf60, 0xf70],
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val_box_freeze: 0x30100,
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val_box_reset: 0x30103,
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val_enable_counting: 0x400000,
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val_select_event: 0x401134,
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val_filter: 0xfe0020,
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val_box_unfreeze: 0x30000,
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};
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// TODO find appropriate values
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const ALDER_LAKE_TO_RAPTOR_LAKE_CORE: CorePerfCounters = CorePerfCounters {
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max_slice: 10,
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msr_unc_perf_global_ctr: 0x2ff0,
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val_enable_ctrs: 0, // TODO
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msr_unc_cbo_perfevtsel0: &[0x2000, 0x2008, 0x2010, 0x2018, 0x2020, 0x2028, 0x2030, 0x2038, 0x2040, 0x2048],
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msr_unc_cbo_per_ctr0: &[0x2002, 0x200a, 0x2012, 0x201a, 0x2022, 0x202a, 0x2032, 0x203a, 0x2042, 0x204a],
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val_disable_ctrs: 0, // TODO
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val_select_evt_core: 0, // TODO
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val_reset_ctrs: 0, // TODO
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};
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// TODO verify his on ICELAKE, and appropriate values. Also deal with backport Cypress Cove ?
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const CANNON_LAKE_TO_TIGER_LAKE_CORE: CorePerfCounters = CorePerfCounters {
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max_slice: 8, // TODO
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msr_unc_perf_global_ctr: 0xe01,
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val_enable_ctrs: 0, // TODO
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msr_unc_cbo_perfevtsel0: &[0x700, 0x708, 0x710, 0x718, 0x720, 0x728, 0x730, 0x738],
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msr_unc_cbo_per_ctr0: &[0x702, 0x70a, 0x712, 0x71a, 0x722, 0x72a, 0x732, 0x73a],
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val_disable_ctrs: 0x0, // TODO
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val_select_evt_core: 0, // TODO
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val_reset_ctrs: 0x0, // TODO
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};
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const SKYLAKE_KABYLAKE_CORE: CorePerfCounters = CorePerfCounters {
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max_slice: 7,
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msr_unc_perf_global_ctr: 0xe01,
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val_enable_ctrs: 0x20000000,
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msr_unc_cbo_perfevtsel0: &[0x700, 0x710, 0x720, 0x730, 0x740, 0x750, 0x760],
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msr_unc_cbo_per_ctr0: &[0x706, 0x716, 0x726, 0x736, 0x746, 0x756, 0x766],
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val_disable_ctrs: 0x0,
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val_select_evt_core: 0x408f34,
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val_reset_ctrs: 0x0,
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};
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const SANDYBRIDGE_TO_BROADWELL_CORE: CorePerfCounters = CorePerfCounters {
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max_slice: 0,
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msr_unc_perf_global_ctr: 0x391,
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val_enable_ctrs: 0x2000000f,
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msr_unc_cbo_perfevtsel0: &[0x700, 0x710, 0x720, 0x730],
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msr_unc_cbo_per_ctr0: &[0x706, 0x716, 0x726, 0x736],
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val_disable_ctrs: 0x0,
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val_select_evt_core: 0x408f34,
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val_reset_ctrs: 0x0,
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};
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