10 lines
289 B
Plaintext
10 lines
289 B
Plaintext
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On Nehalem :
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Bit 1 L2 Prefetcher
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Bit 2 L2 Adjacent Cache line
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Bit 3 L1 DCU next cache line
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Bit 4 L1 IP based prefetcher
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This is confirmed for Sandy Bridge in Table 2-20, which is supported by most processors of later generation (up to KabyLake at least)
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For strides, consider f, e and 7
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